The present invention relates to a system and a method of evaluating a universal serial bus function, and more particularly to a system and a method of evaluating universal serial bus function as peripheral device of personal computer, for example, printer and scanner.
FIG. 1 is a schematic view illustrative of a conventional system of evaluating function of universal serial buses as peripheral devices of personal computer, for example, printer and scanner. The word “universal serial bus” will hereinafter be referred to as “USB”. The conventional system has a computer 101 for controlling an USB function evaluator in accordance with an evaluation test pattern programming software 102. The computer 101 performs conversion to binary data to generate token in accordance with the evaluation test pattern programming software 102. The conventional system has a parallel interface 103 and an USB function evaluator 104 which is connected through the parallel interface 103 to the computer 101. The token generated by the computer 101 is transferred through the parallel interface 103 to the USB function evaluator 104 for storing the token into the USB function evaluator 104. The conventional system also has an USB cable 106, an USB protocol monitor 105 and an USB function 107. The computer 101 is connected through the USB cable 106 to the USB function 107, wherein the USB protocol monitor 105 is provided on an intermediate point of the USB cable 106 for monitoring packets on the USB cable 106. Upon tuning a start switch ON of the USB function evaluator 104, the token is transmitted from the USB function evaluator 104 through the USB cable 106 to the USB function 107, during which the USB protocol monitor 105 provided on the USB cable 106 monitors packets on the USB cable 106 for allowing the USB function evaluator 104 to evaluate the USB function 107.
FIG. 2 is a block diagram illustrative of an internal configuration of the USB function evaluator in the conventional system of FIG. 1. The USB function evaluator 104 has a first channel selector 113, a memory 108, a second channel selector 114, a token transmitter circuit 109, and an oscillator 110. The token is transmitted from the computer 101 to the USB function evaluator 104. The token is stored in the memory 108. When a start switch 112 turns ON, a clock signal is transmitted from the oscillator 110 to the token transmitter circuit 109, whereby the token is transmitted from the token transmitter circuit 109 through an USBI/O buffer 111 to the USB function. The memory 108 has plural independent channel areas for independently storing individual tokens for individual tests. It the token from the computer 101 first enters into the first channel selector 113 for allowing the first channel selector 113 to select one of plural channels so that the token is stored into a selected one of the plural independent channel areas of the memory 108. The second channel selector 114 is provided for selecting one of plural channels so that the token stored in the selected one of the plural independent channel areas of the memory 108 is read out and then transmitted by the token transmitter circuit 109 through the USBI/O buffer 111 to the USB function. The above channel selection function of the USB function evaluator 104 promotes to reduce the number of writing token data in the memory 108.
The above conventional technique, however, has the following problems. The, first problem is that if the computer 101 conducts the test pattern programming, it is necessary to estimate or presume a packet length of a return packet from the USB function having received the token transmitted from the USB function evaluator 104, in order to set a sufficient idling time before the next token for avoiding the next packet from confliction with the return packet.
FIG. 3 is a diagram illustrative of the above-described first problem engaged with the conventional system. First, SetUp token is inputted (P1) to estimate ACK (normal response P2) as the return from the USB function for setting five idol time. Second, IN token is inputted (P4) to estimate return data packet of eight bytes (p8). In this case, in order to avoid confliction between the ACK token and the eight byte data, 120 idol time is set (P6). Third, IN token is inputted (p8) to estimate return data of two bytes (p9). In this case, in order to avoid confliction between the ACK token and the two byte data, 60 idol time is set (P10).
The second problem is that if the computer 101 performs the test pattern programming, it is necessary to estimate the time for completion of preparation by the USB function for the packet return for subsequent setting the return number or the idol time of the IN token. If the USB function accommodates a CPU performing a firmware process to return the data packet, then the necessary time for completing the preparation of the return data depends upon the performance and load state of the CPU of the USB function. It is necessary to return an NAK (response refuse) against the IN token until the preparation of the return data has been completed.
FIG. 4 is a diagram illustrative of the above-described second problem engaged with the conventional system of FIG. 1. At the time of transmission of IN token, the firmware process (S2) of the USB function has not completed the preparation of the return data, for which reason the NAK packet (P5) is returned from the USB function. At the time of transmission of the next IN token (P7), the firmware process (S2) of the USB function has not yet completed the preparation of the return data, for which reason the NAK packet (p8) is returned from the USB function. At the time of transmission of the IN token (P10), the firmware process (S3) of the USB function has already completed the preparation of the return data, for which reason the 8-bytes data packet is thus returned from the USB function. In this case, if the necessary time for the firmware process (S2) is not estimated, this makes it difficult to decide the program number (S1) if the IN token.
If at the worst, the estimation is incorrect so that the program number of the IN token is insufficient for the firmware process, the eight bytes data (P11) is not returned which should have to be returned, and then the test pattern enters into the nest step.
In Japanese laid-open patent publication No. 61-212137, there is disclosed another known technique as the other conventional. USB function evaluator for solving the above described first problem wherein a looped transmission system having a polling interval adjustment means for adjusting the polling interval in accordance with the number of the received cast data FIG. 5 is a diagram illustrative of a transmission timing of the known technique looped transmission system having the polling interval adjustment means. One packet comprises a flag-code (F), address (A), commend (C), frame-check code (FCS), and termination code (GA). The polling interval is changed or adjusted in accordance with the number of texts of the received text data for the purpose of relaxation of increase of traffic and ensure the necessary time for processing the received data.
FIG. 6 is a block diagram illustrative of the polling interval adjusting circuit provided in the looped transmission system. The polling interval adjusting circuit has a receiving shift register 201 for performing serial/parallel conversions of the received data. The polling interval adjusting circuit also has a flag detector circuit 203 being connected to the receiving shift register 201 for detecting the flag code (F). The polling interval adjusting circuit also has a GA detector circuit 202 being connected to the receiving shift register 201 for detecting the termination code (GA). The polling interval adjusting circuit also has an up-down counter 206 being connected to the flag detector circuit 203. As shown in FIG. 5, if one packet has plural number of the test data, the same number of the flag codes are present. The flag code detector circuit 203 detects the plural number “n” of the flag code (F) to count-up by n-times the up-down counter 206. The polling interval adjusting circuit also has a first latch circuit 204 connected to the GA detector circuit 202. The end of the packet is detected by the GA detector circuit 202 and then the packet is held in the first latch circuit 204. An oscillator 205 is provided for supplying a clock. A first logic gate 211 is provided which has two inputs connected to the first latch circuit 204 and the oscillator 205 and a single output connected to the up-down counter 206. A second latch circuit 207 is provided. A second logic gate 212 is also provided which has two inputs connected to the first latch circuit 204 and the up-down counter 206 and a single output connected to the second latch circuit 207. During when the first latch circuit 204 holds the packet, the first and second logic gates 211 and 212 are placed in open state, whereby the up-down counter 206 already counted up is then subjected to a count down by a clock (period T2) which has been supplied from the oscillator 205 through the first logic gate 211. At counting “0”, the up-down counter 206 outputs a carry which is then transmitted through the second logic gate 212 to the second latch circuit 207, whereby the carry is then held by the second latch circuit 207. Upon output of the carry from the up-down counter 206, the first and second logic gates 211 and 212 are placed into close state. An output delay circuit 208 is also provided which is connected to the second latch circuit 207 for receiving the output of carry from the second latch circuit 207 and delaying the transmission timing of the output from the second latch circuit 207 with a predetermined delay time “T1”. A polling generator 209 is further provided which is connected to the delay circuit 208 for receiving the output from the output delay circuit 208 at a delayed timing, so that the polling generator 209 is thus started with a time interval (T1+nT2) from the end of the packet.
If the polling interval adjusting circuit is applied to the USB function evaluator, then it is possible to capture the return packet from the USB function for detecting the end of the received data, whereby automatically the next token may be transmitted without confliction to the returned packet and independently from the length of the returned data. As a result, the above described first problem could be solved, whilst the above described second problem could not be solved because it is necessary to judge whether the returned packet is NAK or data STALL type for plural times of the IN token transmissions. Namely, the above other conventional technique dislocated in the above Japanese publication further needs a further function for judging the kinds of the received packets for controlling the poling generator in accordance with the kind of the packet. Namely, the above other conventional technique dislocated in the above Japanese publication is incapable of solving the above described second problem.
Considering how to solve the second problem, it is difficult to estimate the necessary time for the F/W processes of the USB function. For this reason, it is necessary to optionally set a provisional idol time, otherwise to optionally set the number of IN token so that the test pattern is once executed to the USB function and then the return timing from the USB function is fed back to the above test pattern for correcting the same. Namely, two times executions of each test pattern are necessary. This means that a tremendously long time is taken to prepare the test patterns and subsequent evaluations using the same. Further, if the test pattern once prepared is used for other evaluation to the other USB function, then it is necessary to correct the test pattern because of difference in F/W processing time due to difference of CPU performance and application.
In the above circumstances, it had been required to develop a novel method and system for evaluating USB function free from the above problem.